from the United States District Court for the District of
Delaware in No. l:15-cv-00789-RGA, Judge Richard G. Andrews.
Richard Charles Weinblatt, Stamoulis & Weinblatt LLC,
Wilmington, DE, argued for plain tiff-appellant. Also
represented by STAMATIOS Stamoulis.
Maximilian A. Grant, Latham & Watkins LLP, Washington,
DC, argued for defendant-appellee. Also represented by
GABRIEL BELL; RICHARD GREGORY FRENKEL, Menlo Park, CA.
O'Malley, Hughes, and Stoll, Circuit Judges.
Memory, LLC appeals the district court's dismissal of its
patent infringement complaint against NVIDIA Corporation. The
district court held that Visual Memory's U.S. Patent No.
5, 953, 740 is drawn to patent-ineligible subject matter, and
therefore its complaint failed to state a claim under Federal
Rule of Civil Procedure 12(b)(6). We conclude instead that
the '740 patent claims an improvement to computer memory
systems and is not directed to an abstract idea. Accordingly,
we reverse the district court and remand for further
'740 patent teaches that computer systems frequently use
a three-tiered memory hierarchy to enhance performance. The
three tiers include: 1) a low-cost, low-speed memory, such as
a magnetic disk, for bulk storage of data; 2) a medium-speed
memory that serves as the main memory; and 3) an expensive,
high-speed memory that acts as a processor cache memory.
'740 patent col. 111. 54-64. Because the cache memory is
the most expensive, it is typically smaller than the main
memory and cannot always store all the data required by the
processor. The memory hierarchy alleviates the limitations
imposed by the cache's size because it allows code and
non-code data to be transferred from the main memory to
the cache during operation to ensure that the currently
executing program has quick access to the required data.
Replacement algorithms determine which data should be
transferred from the main memory to the cache and which data
in the cache should be replaced. As a result, the code and
non-code data to be executed by the processor are continually
grouped into the cache, thereby facilitating rapid access for
the currently executing program.
prior art memory systems lacked versatility because they were
designed and optimized based on the specific type of
processor selected for use in that system. Designing a
different memory system for every processor type is
expensive, and substituting any other type of processor into
the system would decrease its efficiency. Memory systems
could be designed to operate with multiple types of
processors, but the design tradeoffs often diminished the
performance of one or all of the computers.
'740 patent purports to overcome these deficiencies by
creating a memory system with programmable operational
characteristics that can be tailored for use with multiple
different processors without the accompanying reduction in
performance. It discloses a main memory 12 and three separate
caches: internal cache 16, pre-fetch cache 18, and write
buffer cache 20. Id. at col. 3 11. 34-53. A
schematic of the '740 patent's memory system is shown
below in Figure 1:
three caches possess programmable operational characteristics
that are programmable based on the type of processor
connected to the memory system. When the system is turned on,
information about the type of processor is used to
self-configure the programmable operational characteristics.
For example, depending on the type of processor, internal
cache 16 can store both code and non-code data, or it can
store only code data. Id. at col. 4 11. 30-35.
Similarly, write buffer cache 20 can be programmed to buffer
data "solely from a bus master other than the system
processor, " or to buffer "data writes by any bus
master including the system processor." Id. at
col. 4 11. 35-43. By separating the functionality for the
caches and defining those functions based on the type of
processor, the patented system can "achieve or exceed
the performance of a system utilizing a cache many times
larger than the cumulative size of the subject caches."
Id. at col. 411. 24-26.
programmable operational characteristic based on the
processor type can also improve the main memory. Fast page
mode is a well-known technique for speeding up access to main
memory. In fast page mode, a row in a memory page is accessed
without having to continually re-specify the row address,
thereby reducing access time. A register associated with the
main memory holds the page address of the most recently
accessed page. The '740 patent's main memory
constitutes an advance over the prior art fast page mode
memory because it is divided into pages containing either
code or non-code data, and "the system provides a bias
towards code pages or non-code pages depending upon the type
of processor connected to the system." Id. at
col. 4 11. 55-58. For one processor type, the register will
hold the address of the most recently accessed code page; for
another processor type, the register will hold the address of
the most recently accessed non-code page. The specification
discloses that combining the selective open page bias with
the fast page mode offers faster access to main memory and
increases system performance. Id. at col. 5 11. 6-8.
together, the "multiple mode operation" of the
'740 patent confers a substantial advantage by
"allow[ing] different types of processors to be
installed with the [same] subject memory system without
significantly compromising their individual
performance." Id. at col. 5 11. 25-29. The
'740 patent's claims reflect these technological
improvements. For example, claim 1 recites:
1. A computer memory system connectable to a processor and
having one or more programmable operational characteristics,
said characteristics being defined through configuration by
said computer based on the type of said processor, wherein
said system is connectable to said processor by a bus, said
a main memory connected to said bus; and
a cache connected to said bus;
wherein a programmable operational characteristic of said
system determines a type of data ...